The present invention relates to a switching circuit.
A switching circuit used in a DC-DC converter, an inverter, or the like has various requirements, such as small size and a small number of components, low ON resistance, low switching loss, and a low surge voltage.
A switching circuit such as that described above uses MOSFETs, IGBTs, or the like. The switching circuit switches these transistors between an ON state and an OFF state by switching a gate voltage applied to the gate terminal, or in other words, a gate electrode, of each transistor. The speed of the switch, or in other words, the switching speed, is dependent on the parasitic capacity of the transistors, or in other words, the input capacity Ciss, the feedback capacity Crss, the output capacity Coss, as well as the resistance value of the gate resistor connected to the gate terminal. The input capacity Ciss is the sum of the gate-source capacity Cgs and the gate-drain capacity Cgd. The feedback capacity Crss corresponds to the gate-drain capacity Cgd, and the output capacity Coss is the sum of the drain-source capacity Cds and the gate-drain capacity Cgd. The switching speed is typically set such that the surge voltage, which is generated by the inductance of an external circuit connected to the transistors, does not exceed the withstand voltage of the transistors. A surge voltage Vsu is determined from the following relational expression using inductance L and switching speed di/dt.Vsu=Ldi/dt 
This equation shows that in order to keep the surge voltage Vsu low, it is necessary to perform at least one of lowering the inductance L and reducing the switching speed di/dt. The inductance L is a value determined in accordance with the structure of the switching circuit, and it is therefore difficult to adjust the inductance L. The switching speed di/dt, on the other hand, can be controlled by adjusting the parasitic capacity and the resistance value of the gate resistor, as described above.
However, when the switching speed di/dt is reduced excessively with the aim of protecting the transistors from the surge voltage, another problem arises in that the switching loss at the switching circuit increases. Further, the parasitic capacity Ciss, Crss, Coss of the transistors varies according to the applied voltage, and therefore the switching speed di/dt must be adjusted taking this variation into account.
Another method of suppressing the surge voltage is to connect a snubber circuit between the drain and the source of the transistor, for example. However, a switching circuit for controlling a large amount of power (large current) requires a snubber circuit having large capacity, and therefore the overall cost of the switching circuit increases.
Japanese Laid-Open Patent Publication No. 2009-296216 discloses a switching circuit for reducing high-frequency noise and reducing an increase of switching loss. The switching circuit connects a drain electrode as a high voltage electrode of a transistor with a gate electrode, i.e., a gate terminal via a variable capacitor. Thus, for example, as the voltage between the drain electrode and the gate electrode increases, the prior art reduces the capacity of the capacitor.
An objective of the present invention is to provide a switching circuit that is capable of reducing switching loss and suppressing a surge voltage while controlling a large current with a compact configuration having a small number of components.